SPIE=INTBLOCK, MSTR=SLAVE, CPOL=SCK_IS_ACTIVE_HIGH_, CPHA=FIRST_EDGE, BITS=16_BITS_PER_TRANSFER, LSBF=MSB
SPI Control Register. This register controls the operation of the SPI.
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |
| BITENABLE | The SPI controller sends and receives 8 bits of data per transfer. 1 (THE_SPI_CONTROLLER_S): The SPI controller sends and receives the number of bits selected by bits 11:8. |
| CPHA | Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending. 0 (FIRST_EDGE): Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal. 1 (SECOND_EDGE): Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active. |
| CPOL | Clock polarity control. 0 (SCK_IS_ACTIVE_HIGH_): SCK is active high. 1 (SCK_IS_ACTIVE_LOW_): SCK is active low. |
| MSTR | Master mode select. 0 (SLAVE): The SPI operates in Slave mode. 1 (MASTER): The SPI operates in Master mode. |
| LSBF | LSB First controls which direction each byte is shifted when transferred. 0 (MSB): SPI data is transferred MSB (bit 7) first. 1 (LSB): SPI data is transferred LSB (bit 0) first. |
| SPIE | Serial peripheral interrupt enable. 0 (INTBLOCK): SPI interrupts are inhibited. 1 (HWINT): A hardware interrupt is generated each time the SPIF or MODF bits are activated. |
| BITS | When bit 2 of this register is 1, this field controls the number of bits per transfer: 0 (16_BITS_PER_TRANSFER): 16 bits per transfer 8 (8_BITS_PER_TRANSFER): 8 bits per transfer 9 (9_BITS_PER_TRANSFER): 9 bits per transfer 10 (10_BITS_PER_TRANSFER): 10 bits per transfer 11 (11_BITS_PER_TRANSFER): 11 bits per transfer 12 (12_BITS_PER_TRANSFER): 12 bits per transfer 13 (13_BITS_PER_TRANSFER): 13 bits per transfer 14 (14_BITS_PER_TRANSFER): 14 bits per transfer 15 (15_BITS_PER_TRANSFER): 15 bits per transfer |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |